I2C Bus Protocol
I2C bus uses two lines – SDA (Serial Data line) and SCL (Serial Clock line). Every device connected to the I2C bus can operate as either I2C master (generates the clock and initiates communication with slaves) or I2C slave (responds when addressed by the master).
DLN-series adapters can operate as master devices (read I2C Master Interface). Some DLN adapters can also operate as slave devices (read I2C Slave Interface).
The I2C bus is a bidirectional bus, but this does not mean that the data is transmitted in both directions simultaneously. At every particular moment, either master or slave sends data over the I2C bus. The device that sends data to the bus is called Transmitter. The device that receives data from the bust is called Receiver. Most I2C devices can both transmit and receive data. However, some I2C devices are only able to receive data. DLN adapters are capable of transmitting and receiving data.
The I2C bus is a multi-master bus; that means that any number of master devices can be present. The DLN-series adapters support clock synchronization and arbitration to avoid conflicts with other master devices on the same I2C bus. Read Avoiding Conflicts in a Multi-master I2C Bus for details.
The maximum number of slave devices is limited by the address space. Each slave device has a unique address. The I2C bus can use 7 or 10-bit addressing. The DLN-series adapters use 7-bit addressing.
Data Transmission
Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull-up resistor.
All the devices connected to the I2C bus must have an open-drain (or open-collector) output stages – they can either pull the bus low or be in high-impedance. When there is no data transmission on the I2C bus, both lines are HIGH. In this case, we say that the I2C bus is free.
I2C master generates clock signal on the SCL line. One SCL pulse is generated for each data bit. The data on the SDA line must be stable during the HIGH period of the clock (while SCL line is high). The changes on the SDA line occur when the SCL line is LOW. The only exception from this rule are START, STOP and Repeated START Conditions described later.
Byte Format and Acknowledge Bit
Every byte, sent over the I2C bus, is eight bits long. Data is transferred with the Most Significant Bit (MSB) first. An Acknowledge bit must follow each byte. The master generates all clock pulses, including the acknowledge clock pulse.
The Acknowledge bit allows:
The receiver to signal the transmitter that the byte was successfully received and another byte may be sent;
The receiver to signal the transmitter that it received enough data and the transmission should be terminated;
The slave to signal the master that the specified slave address is present on the bus and transmission can start (see Slave Address and Data Direction);
The slave to delay the transmission, while it prepares for another byte of data (see Clock Stretching for details).
After transmission of the last eighth bit of data, the transmitter releases the SCL line (during the low phase of clock). This gives an opportunity to receiver to acknowledge (or not acknowledge) the data.
If the receiver pulls the line LOW during the HIGH period of the ninth clock pulse, it acknowledges the byte (the Acknowledge (ACK) signal).
The Not Acknowledge (NACK) signal is defined when SDA remains HIGH during this clock pulse. The master then can generate either a STOP (P) condition to abort the transmission, or a repeated START (Sr) condition to start a new transmission.
The following conditions can lead to the Not Acknowledged (NACK) signal:
There is no device to acknowledge the slave address – no slave with the specified address is connected to the I2C bus.
The slave is unable to receive or transmit – it is busy performing another function.
The slave does not support the specified data direction (read or write).
The receiver gets data that it does not understand.
The receiver cannot receive any more data bytes.
A master-receiver must signal the end of the transmission to the slave-transmitter.
I2C Transaction
The data transmission includes the following steps:
The master initiates communication by generating a START (S) Condition;
The master sends the first byte that includes a Slave Address and Data Direction;
The slave generates the acknowledgement (ACK) signal. If the master receives no acknowledgement signal, it generates the STOP (P) condition to terminate the transmission.
The transmitter (master or slave) writes a byte of data to the bus and the receiver (slave or master) reads this byte of data from the bus.
After each byte of data, the receiver sends the acknowledgement (ACK) signal and the transmission continues. If the receiver sends no acknowledgement signal, the transmitter stops writing data to the I2C bus.
To terminate transmission, the master generates the STOP (P) Condition. To change transmission parameters, the master generates the Repeated START (Sr) Condition.
START, STOP and Repeated START Conditions
All transactions begin with a START (S) condition and finish with a STOP (P) condition.
START (S) Condition
To generate a START condition, the master changes the SDA line from one to zero while the SCL line is HIGH (marked in red on the following diagram). The I2C bus is considered busy after the START condition. To prepare the bus for transmission of the first bit, the master outputs zero on the SCL line (marked in green).
STOP (P) Condition
To generate a STOP condition, the master changes the SDA line from zero to one while the SCL line is HIGH (marked in red). The I2C bus is considered free after the STOP condition. To prepare for the STOP condition, the master sets the SDA line to zero during the LOW phase of the SCL line (marked in green).
Repeated START (Sr) Condition
Instead of the STOP condition, the master can generate a repeated START (Sr) condition. Like a START condition, to generate a repeated START condition, the master changes the SDA line from one to zero while the SCL line is HIGH (marked in red). In this case, the I2C bus remains busy. To prepare for the repeated START condition, the master sets the SDA line to one during the LOW phase of the SCL line (marked in green).
The START (S) and repeated START (Sr) conditions are functionally identical. The repeated start conditions is used in the following situations:
To continue transmission with the same slave device in the opposite direction. After the repeated START condition, the master sends the same slave device address followed by another direction bit.
To start transmission to or from another slave device. After the repeated START condition, the master sends another slave address.
To provide a READ operation from internal address. See READ Operation for details.
DLN adapters use the repeated START condition to read from the internal address (the DlnI2cMasterRead() function) and to write to and then read from the same slave device (the DlnI2cMasterTransfer() function). If a DLN adapter needs to communicate with different slaves, it finishes one transmission (with the STOP condition) and starts another transmission.
Slave Address and Data Direction
Every byte on the SDA line must be eight bits long. The first byte after START contains seven bits of the slave device address and one bit that defines the direction of the transmission.
As any other data, the address is transmitted sequentially starting with the Most Significant Bit (MSB) and ending with the Least Significant Bit (LSB).
The direction bit has the following values:
0 – Write: the master transmits data to the slave;
1 – Read: the master receives data from the slave.
Reserved I2C Slave Addresses
There are 16 reserved I2C addresses. The following table shows the purposes of these addresses:
| I2C slave address | Direction bit (R/W) | Description |
0000 000 | 0 | General call address |
0000 000 | 1 | START byte |
0000 001 | X | CBUS address |
0000 010 | X | Reserved for different bus format |
0000 011 | X | Reserved for future purposes |
0000 1XX | X | Hs-mode master code |
1111 1XX | 1 | Device ID |
1111 0XX | X | 10-bit slave addressing |
The general call address is for addressing all devices connected to the I2C bus. If a device does not need the provided data, it can ignore this address (it does not issue the acknowledgement). If a device requires data from a general call address, it acknowledges this address and behaves as a slave-receiver. If one or more slaves acknowledge the general call address, the master does not know how many devices did it and does not see not-acknowledged slaves.
If you use a DLN-series adapter as I2C slave, you can configure it to support general call addressing or to ignore it.
Using Internal Addresses
Some I2C slave devices have fixed internal address setting. The internal address is the slave’s internal register. Possible internal addresses depend on the slave device. Some very simple devices do not have any, but most do.
To communicate with a certain register, after the I2C master addressed the slave device and received acknowledgement, it sends the internal address inside the slave where it wants to transmit data to or from.
Both read and write operations can use an internal address. When an internal address is set, the same address is used in every READ and WRITE operations that follows the previous operation.
WRITE Operation
To write to a slave device, the I2C master follows these steps:
Sends the START (S) condition.
Sends the I2C address of the slave device.
Sends the WRITE (W) direction bit.
Receives the acknowledgement (ACK) bit.
Sends the internal address where it wants to write.
Receives the acknowledgement (ACK) bit.
Sends data bytes and receives the acknowledgement (ACK) bit after each byte.
Sends the STOP (P) condition.
To write data using internal address, call the DlnI2cMasterWrite() function. It requires the slave device address (the slaveDeviceAddress parameter), the length of the internal address (the memoryAddressLength parameter) and the internal address (the memoryAddress parameter).
READ Operation
Before reading data from the slave device, the master tells the slave which of the internal addresses it wants to read. Therefore, a read operation starts by writing to the slave.
To read from a slave device, the I2C master follows these steps:
Sends a START (S) condition.
Sends the I2C address of the slave device.
Sends the WRITE (W) direction bit.
Receives the acknowledgement (ACK) bit.
Sends the internal address where it wants to read from.
Receives the acknowledgement (ACK) bit.
Sends the repeated START (Sr) condition.
Sends the READ (R) direction bit.
Receives the acknowledgement (ACK) bit.
Receives data bytes and sends acknowledgement (ACK) bits to continue reading or a not acknowledgement (NACK) bit to stop reading.
Sends the STOP (P) condition.
To read data using internal address, call the DlnI2cMasterRead() function. It requires the slave device address (the slaveDeviceAddress parameter), the length of the internal address (the memoryAddressLength parameter) and the internal address (the memoryAddress parameter).
Avoiding Conflicts in a Multi-master I2C Bus
In a multi-master I2C bus, the collision when more than one master simultaneously initiate data transmission is possible. To avoid the chaos that may ensue from such an event, DLN adapters, like all I2C master devices, support clock synchronization and arbitration. These procedures allow only one master to control the bus; other masters cannot corrupt the winning message.
Clock synchronization allows to perform the level on the SCL line. Arbitration determines which master completes transmission. If a master loses arbitration, it turns off its SDA output driver and stops transmitting data.
Slaves are not involved in clock synchronization and arbitration procedures.
Clock Synchronization
A DLN adapter and one or more I2C masters can begin transmitting on a free I2C bus at the same time. Each master generates its own clock on the SCL line. Therefore, there must be a method for deciding which master generates LOW and HIGH periods of the SCL line. Clock synchronization does it.
Once a DLN adapter or any other I2C master outputs LOW on its clock line, the SCL line goes LOW. When a master releases its clock line, the SCL line goes HIGH only if no other master has its clock line in LOW state. The master with the longest LOW period holds the SCL line in LOW state. Masters with shorter LOW periods stay in a HIGH wait-state during this time.
When all masters concerned have released their clock lines, the SCL line goes HIGH and all the masters start counting their HIGH periods. The first master that completes its HIGH period pulls the SCL line LOW again.
Therefore, the master with the longest clock LOW period determines a LOW period on the SCL line; the master with the shortest clock HIGH period determines a HIGH period on the SCL line.
The following figure shows clock synchronization for the DLN adapter and the Master2 device. The DLN adapter has a shorter HIGH period; it pulls the SCL line LOW. The Master2 device has a longer LOW period, only when it releases its clock line, both masters start counting HIGH period.
Arbitration
Arbitration, like clock synchronization, is required only if more than one master is used in the system. A master may start transmission only if the bus is free. A DLN adapter and one or more other masters may generate a START condition within the minimum hold time, which results in a valid START condition on the bus. Arbitration is then required to determine which master will complete its transmission.
Arbitration proceeds bit by bit. During every bit, while SCL is HIGH, each master checks to see if the SDA level matches what it has sent. If at least one master outputs LOW, the SDA line will have the LOW level. If a master changes the state of the SDA line to HIGH, but the line stays in LOW, then this indicates that this master lost arbitration and it needs to back off.
The arbitration process may take many bits. More than one masters can even complete an entire transaction without error if their transmissions are identical.
A master that loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration and can restart its transaction when the bus is free.
If a master can act as a slave and it loses arbitration during the addressing stage, it must switch immediately to its slave mode because the winning master may try to address it.
The following figure shows the arbitration procedure for the DLN adapter and the Master2 device. The moment when there is a difference between the DATA1 level and the actual level on the SDA line, the DLN adapter switches off the DATA1 output.
Clock Stretching
In an I2C communication, a master device determines the clock speed. The I2C bus provides an explicit clock signal that relieves a master and a slave from synchronizing exactly to a predefined baud rate.However, some slave devices may receive or transmit bytes of data at a fast rate, but need more time to store a received byte or prepare another byte to be transmitted. Slaves can then hold the SCL line LOW to force the master into a wait-state until the slave is ready for the next byte transmission. This mechanism is called clock stretching. An I2C slave is allowed to hold the SCL line LOW if it needs to reduce the bus speed. The master on the other hand is required to read back the SCL signal after releasing it to the HIGH state and wait until the SCL line has actually gone HIGH. DLN-series adapters support clock stretching. Taking into consideration the impacts of clock stretching, the total speed of the I2C bus might be significantly decreased.